Arista DCS-7130-48LAS-R | 7130LS 48-Port 10G FPGA Switch, VU7P-2, Atomic Clock

SKU:DCS-7130-48LAS-R

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Description

The Arista 7130LS Series is a 1U Layer 1+ FPGA switch built for low-latency trading, exchange connectivity and market data fan-out. It also suits network monitoring and tap aggregation where precise timestamping matters, such as MiFID II and RTS 25 compliance, and it can host custom FPGA applications.

This 48LAS model provides 48 SFP+ ports supporting 100M, 1GbE and 10GbE (100M to 11.3Gbps) plus 2 RJ45 ports. A Xilinx Virtex UltraScale+ VU7P Speed Grade 2 FPGA switches at Layer 1 in 5 ns with under 100 ps jitter, with MetaMux latency of 43 ns and MultiAccess latency of 55 ns. The 'LAS' variant adds an atomic clock. This SKU has rear-to-front airflow and 1+1 redundant hot-swap AC power supplies (2xAC), with a maximum power draw of 430W.

It works with SFP+ optics and cables from 10GBASE-CR and SR through LR, ER and DWDM, plus 40GBASE-CR4 and 1000BASE-T. The matching fan tray is FAN-7130-1U-R and spare power supplies are PWR-500AC-R. FPGA development is supported through the FDK.

Enquire with XS Network Tech for new or used pricing and availability.

Features

- Layer 1 switching in 5 ns with deterministic latency and under 100 ps jitter
- Signal regeneration, media conversion, port mirroring, telemetry and dynamic patching
- Layer 1+ packet statistics on every port
- Completely non-blocking, with the same latency for 1:N port mirroring
- Bit-for-bit forwarding of any protocol
- Integrated FPGA for custom or third-party applications
- Linux-based platform with industry-standard CLI and JSON RPC API
- Embedded influxdb database, eye diagram monitoring, tcpdump on every port, LLDP and full SFP+ diagnostics
- Dual redundant hot-swappable power supplies and fans

Warranty

All products sold by XS Network Tech include a 12-month warranty on both new and used items. Our in-house technical team thoroughly tests used hardware prior to sale to ensure enterprise-grade reliability.

All technical data should be verified on the manufacturer data sheets.

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Technical Specifications

FAQs

Technical Specifications

- Ports: 48 x SFP+ (100M/1GbE/10GbE), 2 x RJ45
- Throughput: 100M to 11.3Gbps per port
- FPGA: Xilinx Virtex UltraScale+ VU7P Speed Grade 2
- Layer 1 latency: 5 ns
- Jitter: less than 100 ps
- MetaMux latency: 43 ns
- MultiAccess latency: 55 ns
- FPGA DRAM: 32GB DDR
- CPU: Quad-Core x86
- System memory: 8GB RAM
- On-board SSD: 64GB
- Clock: Atomic
- Applications: MetaWatch, ExchangeApp, MetaProtect (SwitchApp not supported)
- FPGA Dev Kit (FDK): Yes
- Internal 10G ports: 2
- Management ports: 2 x 100/1000
- PPS input: 1 (5V TTL, 50 ohm)
- PPS output: 1 (5V TTL)
- Serial port: 1 x RS-232 (RJ-45)
- USB ports: 1
- Power supplies: 2 x hot-swap AC, 1+1 redundant
- Fan trays: 2 x hot-swap, 1+1 redundant
- Airflow: Rear-to-front
- Maximum power draw: 430W
- Form factor: 1U
- Dimensions (WxHxD): 44.8 x 4.3 x 37.9 cm
- Weight: 9kg
- Operating temperature: 0 to 40 C
- Relative humidity: 10% to 85% non-condensing
- Maximum altitude: 2,000m

FAQs

Q: Does this switch need a licence for its applications?
A: MetaWatch, ExchangeApp and MetaProtect are supported on this model, while SwitchApp is not. Licensing terms for these applications are set by Arista, so confirm them with Arista or your supplier before deployment.

Q: How is this switch powered?
A: This SKU is the 2xAC configuration with two hot-swap 1+1 redundant PWR-500 AC power supplies. Maximum power draw is 430W.

Q: Which optics and cables does it support?
A: It supports 10GBASE-CR (0.5m to 5m), 10GBASE-SRL, 10GBASE-SR, 10GBASE-LRL, 10GBASE-LR, 10GBASE-ER and 10GBASE-DWDM SFP+ optics, 40GBASE-CR4 cabling and 1000BASE-T.

Q: What airflow direction does this SKU use?
A: This SKU has rear-to-front airflow, so the matching fan tray is FAN-7130-1U-R. Spare power supplies for this airflow are PWR-500AC-R.

Q: How does this model differ from other 7130 variants?
A: This 48LAS model has 48 ports, a VU7P-2 FPGA and an atomic clock, in a rear-to-front airflow, 2xAC power supply configuration.