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Cisco

Cisco UCSX-CPU-A9475F | EPYC 9475F | 48-core 3.65 GHz, 400W TDP, 256MB L3, 12-ch DDR5 (up to 6000 MT/s), PCIe 5.0, SP5 Genoa, freq-optimized

SKU:UCSX-CPU-A9475F

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Description

Top-bin frequency-optimized EPYC 9004 processor tuned for maximum per-core throughput while maintaining a robust 48-core footprint. Ideal for high-frequency trading, real-time analytics, and performance-sensitive application tiers on SP5 platforms with DDR5 and PCIe 5.0.

Features

- Highest frequency 48-core option for peak per-core throughput
- Large 256MB L3 cache to keep hot data close to compute
- 12-channel DDR5 and PCIe 5.0 enable extreme memory bandwidth and I/O
- Robust enterprise RAS features suited for mission-critical deployments

Warranty

All products sold by XS Network Tech include a 12-month warranty on both new and used items. Our in-house technical team thoroughly tests used hardware prior to sale to ensure enterprise-grade reliability.

All technical data should be verified on the manufacturer data sheets.

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FAQs

Technical Specifications

FAQs

Q: What workloads benefit most from 9475F?
A: Latency-sensitive and high-frequency workloads (e.g., trading, in-memory databases, real-time analytics) that leverage higher sustained clocks.

Q: Does it require special cooling?
A: Yes. Use a platform-qualified SP5 cooling solution rated for 400W TDP and ensure proper chassis airflow.

Q: Is DDR5-6000 guaranteed?
A: No. Achievable memory data rate depends on DIMM type, capacity, channel population, and server BIOS support.

Q: Can I deploy in dual-socket servers?
A: Yes, provided the motherboard and system support dual SP5 CPUs and the same SKU is paired across sockets.

Technical Specifications

- CPU family: AMD EPYC 9004 (Genoa)
- Model: 9475F (frequency-optimized)
- Cores / Threads: 48 / 96
- Base frequency: 3.65 GHz
- L3 cache: 256 MB
- TDP: 400 W
- Socket: SP5 (LGA 6096)
- Memory: 12-channel DDR5, up to 6000 MT/s (platform dependent), ECC RDIMM/LRDIMM
- I/O: Up to 128 lanes PCIe 5.0, CXL support
- Process technology: TSMC 5nm
- Instruction set: x86-64 with AVX-512
- Multi-socket support: 1P/2P capable (platform dependent)

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